(1) Field of the Invention
The invention relates to a Class-D Power Amplifier, and more particularly, to a Class-D Power Amplifier having a pulse coded digital input signal and typically using an H-Bridge to drive an output load, like a loudspeaker.
(2) Description of the Prior Art
Class-AB amplifiers are notoriously inefficient and Class-D amplifiers overcome this shortfall. With Class D amplifiers, the output is made to switch between the two output levels at a very high frequencyxe2x80x94substantially higher than the highest audible frequency, which is done by feeding high-frequency pulses to the power amplification stage. Either the pulse-width ratio of the driving signal can be varied at a constant frequency or the pulse density of the driving signal can be varied at a constant pulse width in order to make the averaged (filtered) output signal follow the (amplified) input signal very closely. Such amplifier is referred to as Pulse Width Modulated (PWM) or Pulse Density Modulated (PDM). The output voltage at the load, after passing a low pass filter, represents the input under the assumption of a constant the supply voltage.
In the case of Pulse Density Modulation, the pulse width is always constant, where the high frequency pulses can be generated by for example a Sigma Delta Modulator. The output device, a Class-D driver, can only provide +V or xe2x88x92V or zero, thus limiting the pulse generation to a maximum of 3 levels. This limited number of levels also limits the signal accuracy.
FIG. 1 shows a schematic block diagram of a state-of-the-art PDM Class-D Amplifier. It typically comprises a Sigma Delta Modulator (11) to generate the driving signal for the Class-D power output stage, which is typically an H-Bridge (12) and the output load, often a loudspeaker (13).
FIG. 2a shows a simplified diagram of an H-Bridge and FIG. 2b shows the 3 output signal levels and the corresponding states of the output devices. The output level at the load LOAD is xe2x80x9c+Vxe2x80x9d with Transistor T2 and T3 closed, T1 and T4 open (21); it is xe2x80x9cxe2x88x92Vxe2x80x9d with Transistor T1 and T4 closed, T2 and T3 open (22) and it is xe2x80x9cxc2x10xe2x80x9d with Transistor T1 and T4 closed, T2 and T3 open (23).
U.S. Pat. No. (5,949,282 to Nguyen, Huey, Takagishi, Hideto) describes circuit for, first, generating an accurate reproduction of the output of a Class D amplifier for error-correction purposes, and then, second, comparing the reference signal to the original signal input to the amplifier for error-correcting purposes.
U.S. Pat. No. (5,847,602 to Su, David) shows a delta-modulated magnitude amplifier which is used to amplify the magnitude component of an RF power amplifier that employs envelope elimination and restoration. The delta-modulated amplifier introduces a smaller amount of non-linearity than traditional approaches, which are based upon pulse-width modulation. The disclosed technique can be implemented using switched-capacitor circuits in a standard MOS technology with only two external components, i.e., an inductor and a capacitor. Thus, the disclosed technique allows the implementation of an efficient and yet linear RF power amplifier using low-cost MOS technology.
U.S. Pat. No. (5,974,089 Tripathi, et al) describes an oversampled, noise shaping signal processor having at least one integrator stage in a feedback loop. A sampling stage in the feedback loop is coupled to the at least one integrator stage. The sampling stage samples an analog signal at a sample frequency. Qualification logic coupled to the sampling stage receives a pulse waveform therefrom, and ensures that signal transitions in the pulse waveform occur more than a first time period apart and that the waveform can therefore be handled by, for example, a power switching device. A switching stage in the feedback loop is coupled to the qualification logic. The signal processor has a feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop.
In accordance with the objectives of this invention, a circuit to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels, is achieved. Multi-level pulse widths allow a better quality output signal. Also, using multi-level pulse widths, in contrast to just a single pulse width, allows the reduction of the pulse-sampling rate by the same factor.
A Class-D Amplifier using PDM (Pulse Density Modulation) normally converts the input signal with a Sigma Delta Modulator into high-frequency pulses of equal width. And a Class-D amplifier typically uses an H-Bridge with its 3 switching levels (+V, xe2x88x92V, 0) to drive an output load through a low-pass filter. Typical loads are a loudspeaker or a servo-motor.
The fundamental idea of the disclosed invention is to add the circuits and methods to produce pulses with a multiple of discrete values-of-width and to provide the method to generate a pulse length select signal for these variable-width-pulses. Now the output signal has virtual multi-level pulses with only 3 physical levels.
To achieve this, the processing unit for the input signal converter, typically containing a Sigma Delta Modulator, not only generates the digital signals xe2x80x9cPulse activexe2x80x9d and xe2x80x9cPulse pos/negxe2x80x9d, but also a digital xe2x80x9cPulse length selectxe2x80x9d signal. A xe2x80x9cLength of Pulse Integratorxe2x80x9d Function then takes the pulse start information and starts integrating. When the integrated value reaches a specific reference level, selected by the pulse-length-select signal out of a set of pulse area reference values, the integration stops the output signal pulse and generates the pulse stop information. The proposed circuit may contain different techniques to define a set of output pulse area reference values, one for each step of said multi-level output.
The circuit also comprises a xe2x80x9cPulse Generator Unitxe2x80x9d inserted into the signal path between said converter of PCM signals and the Class-D output power stage, which is, as said before, typically an H-Bridge. Said H-Bridge then drives voltage into said output load.
Further, in accordance with the objectives of this invention, said pulse area reference levels may not only be of fixed level, but may also be externally controlled.
In accordance with the objectives of this invention, a method to generate virtual multi-level output pulses for a Class-D Amplifier, where the time-voltage-area corresponds to a multiple of digital levels, is achieved. First it converts said input signal into ideal PCM control pulses. In addition to said xe2x80x9cpulse activexe2x80x9d and xe2x80x9cpulse polarityxe2x80x9d signal, it also generates said xe2x80x9cpulse length selectxe2x80x9d signal. The proposed method defines said set of output pulse area reference values, one for each step of said multi-level output. The xe2x80x9cLength of Pulse Integratorxe2x80x9d determines said pulse stop time, based on said pulse start time (clock), on said digital xe2x80x9cpulse length selectxe2x80x9d signal and based on said output pulse area reference values. The xe2x80x9cPulse Generator Unitxe2x80x9d generates said multi-level output pulses using said pulse start and pulse stop signals and applies said power driver control pulses to said Class-D power driver. Finally said power driver feeds the output voltage to said output load.